The invention relates generally to semiconductor circuit design and, more particularly, to a method and apparatus for a memory sensing circuit with a constant delay-time.
Digital logic requires input and output signals to meet defined voltage levels to be interpreted as either "high" or "low." However, typical integrated circuits, or "chips," utilizing digital logic also include signals at many voltage levels. As a result, sense amplifying circuits are utilized to interpret, or "separate," the signals, driving them to either a high or low voltage level, thereby producing the correct voltage level for other digital circuits on the chip. For example, a capacitor-type memory cell for a dynamic random access memory ("DRAM") device utilizes very small bit signals. Sense amplifier circuits residing on the DRAM device separate the bit signals by comparing them to a precharge level, which is defined as a level between the high and low levels of the memory cell. If the level of the bit signal is above the precharge level, then the sense amplifier circuit interprets the signal as a high, or logic 1, signal. If the level of the bit signal is below the precharge level, then the sense amplifier circuit interprets the signal as a low, or logic 0, signal.
As technology progresses, the speed and accuracy of the signal separation performed by sense amplifier circuits becomes more critical. For this reason, chip designers have tried various methods to speed up the signal separation. For example, U.S. Pat. No. 5,257,232 to Dhong et al., teaches a method of overdriving sense amplifier circuits to speed up the signal separation. Although this method succeeds in separating the signals quickly, it has drawbacks. One such drawback is that the overdriving is inaccurate because when the sensing is complete, the signals do not return to their desired precharge level. Instead, the signals return to a level that is offset due to the overshot voltage during the sensing. As a result, the precharge level becomes altered, and the sense amplifier circuits do not interpret the next bit signal incorrectly.
This problem is exacerbated by the fact that modem integrated circuits utilize an external power supply ("VDD") that may be set to different voltage levels. For example, a single chip may operate at an external power supply level between 4.0 V and 2.4 V. Therefore, components used by sense amplifier circuits, as well as a length of time in which a signal is overdriven, must support a wide variance in power supply levels. For example, conventional chips utilize a large p-channel common source switch to control the length of time a signal is overdrawn. This is due to the ability of a p-channel device to pull to a very high voltage and to do so quickly at high power supply levels. However, the operational characteristics of p-channel devices vary dramatically with changes in operating voltages, making a fast and accurate design even more difficult to achieve. Furthermore, p-channel devices vary greatly with changes in operating voltages, being very slow at low operating voltages. Further still, p-channel devices require significantly large amounts of layout space on the chip.
Therefore, what is needed is a method and apparatus for overdriving signals to achieve fast signal separation, while maintaining the accuracy of the sense amplifier operation.
Furthermore, what is needed is a method and apparatus for overdriving signals in chips operating at different power supply levels.